1. Field of the Invention
The present invention relates generally to the design of integrated circuits and, more particularly, to the design of circuit components for placement in an integrated circuit layout.
2. State of the Art
A first-in first-out (FIFO) memory device generally includes a plurality of memory cells (e.g., flip-flops) that are arranged to form registers for storing a corresponding number of data bits and for permitting storage of at least one digital word. In addition to memory cells, conventional FIFO memory devices include circuit components for achieving the first-in, first-out operation. For example, FIG. 1 shows a single bit from each of five registers of a conventional FIFO memory device. The memory cells 2, 4, 6, 8 and 10 can each be, for instance, a flip-flop that stores a single bit from each of five words input to the FIFO memory device on data input line 12, labelled "din". If 8-bit words were to be stored in the FIFO memory device, eight rows of flip-flops as shown would be provided.
In operation of the FIFO memory device of FIG. 1, input data on line 12 is shifted through the five registers to data output line 14. Thus, the FIFO memory device operates like a shift register, with data being transferred one register to the right upon the occurrence of each read or write clock pulse on clock input line 16. When writing information into the FIFO memory device or when reading information out, the clock input on line 16 is directly input to flip-flop 10 to place the information stored in flip-flop 10 onto data output line 14. A single clock is therefore used to effect both read and write operations.
Further in the FIFO memory device in FIG. 1, the input signal on clock line 16 is provided to a series of delay gates 18, 20, 22 and 24 to cause a sequential transfer of data to the right, and to ensure that data is not overwritten. The delay associated with each of delay gates 18-24 thus corresponds approximately to the time required for data to be shifted out of one of flip-flops 2-10. Accordingly, after data has been shifted out of flip-flop 10, the signal or clock input line 16 appears at the output of delay gate 18 to clock data out of flip-flop 8 and into flip-flop 10. Subsequently, the signal on clock input line 16 appears at the output of delay gate 20 to clock data out of flip-flop 6 and into flip-flop 8. A sequential transfer of data occurs until any data present on data input line 12 is clocked into flip-flop 2.
Further in the FIFO memory device in FIG. 1, to guarantee that previously stored data will not be overwritten prior to being accessed at data output line 14, the clock signal and the stored data are shifted in opposite directions. That is, data is shifted to the right while the clock signal is shifted to the left. A Texas Instruments document labelled "SN74S225 16.times.5 Asynchronous First-In First-Out Memory" discloses one such device wherein a single clock signal is generated for both read and write operations. Further, a document labelled "CD 54/74 HC 40105 CD 54/74 HCT 40105" discloses another similar device.
A primary constraint of FIFO memory devices such as the one shown in FIG. 1 is that such devices require that the clock delay associated with each memory cell be accurately determined and implemented in the integrated circuit layout. Further, because a single clock performs both read and write operations by strobing data into flip-flop 2 for a write operation and by strobing data out of flip-flop 10 for a read operation, five read/write clock pulses are required before data input to the FIFO memory device can be accessed. Also, if a circuit component connected with data output line 14 is not yet ready to accept information from the FIFO memory device upon occurrence of a read or write clock pulse, the data output from flip-flop 10 could be lost unless additional control logic is provided at the FIFO memory device output to accommodate such a situation.
Yet another known FIFO memory device is shown in FIGS. 2A and 2B, wherein single memory cells for each of four registers are depicted as elements 26, 28, 30 and 32 in FIG. 2A. In this architecture, a ring counter such as that of FIG. 2B is used to address one of the memory cells of FIG. 2A via write lines 27, 29, 31 and 33 or one of read address lines 44, 46, 48 and 50. Data is written into an addressed one of the FIG. 2A memory cells via data input line 23 (labelled "din"). Data is read out of one of the memory cells via data output line 25 (which has a load capacitance "C", and is labelled "dout").
To select one of write address lines 27, 29, 31, or 33 during a write operation of the FIFO memory device of FIGS. 2A, a ring counter as shown in FIG. 2B can be employed. A similar counter is provided for selecting one of read address lines 44, 46, 48 or 50. Because of the similarity of the two ring counters required, only a ring counter for selecting the read address lines of the FIG. 2A memory cells will be described. A document labelled "SN54ALS233 A, SN74ALS233 A 16.times.5 Asynchronous First-In, First-Out Memories" discloses a FIFO memory device which employs addressing via a ring counter technique.
As with the FIG. 1 circuit, a read (or write) clock signal is sequentially input via clock input line 34 and delay gates 36, 38 and 40, to each of four flip-flops 35, 37, 39 and 41. The FIG. 2B ring counter is initialized via reset line 42 to a 4-bit binary value of "1000", for example, with each of the bits in this binary value corresponding to an address for one of the FIG. 2A memory cells. During proper operation, the FIG. 2A memory cell being selected by the FIG. 2B flip-flop possessing the "1" is considered "active". With each read (or write) clock pulse on clock input line 34, the "active" flip-flop passes the "1", which serves an a "active pointer" to identify the next sequential FIG. 2A memory cell (i.e., "1000"-"0100"-"0010"-"0001"-"1000"). Thus, the FIG. 2B circuit functions like a ring counter whereby each of memory cells 26-32 is sequentially activated via the active pointer and clock input line 34. As each memory cell is addressed, data is read from (or written into) the memory cell via address lines 44, 46, 48 and 50. Because no shifting of data among memory cells occurs, two separate read and write pointers are required to identify the "active" read memory cell and the "active" write memory cell.
In practice, the FIFO memory device of FIG. 2 has data accessing problems similar to those of the memory device of FIG. 1. That is, delays associated with accessing information exist due to the read/write pointer generation. Because data is no longer shifted, overwrite concerns are essentially eliminated. However, address data output line 25 is typically a shared bus which possesses load and wire interconnect RC delays when driving the output to a different state (e.g., high to low, or vice versa). Thus, whenever a new address is provided, the data output from the addressed memory cell must charge (or discharge) a bus connecting data lines for each of memory cells 26-32 to the new output value. Accordingly, output to the shared bus can possess more than two states in transitioning from a low to a high value, or vice versa, due to the connection of plural driving devices such as memory cells to a common bus. Because a common output bus is used, each memory cell has to drive the buffer directly connected to the outputs of all four FIG. 2A memory cells. This increased load can be represented as the increased capacitance "C" shown at the memory cell outputs, and involves a relatively large charging-time constant. Thus, in addition to access timing delays associated with pointer operation, the FIG. 2 FIFO memory device includes access delays due to output charging time. The greater the number of registers included in the FIFO memory device, the greater these delays become. With a larger number of registers, a larger number of ring counter addresses must be provided and a greater load will be associated with the output bus.
Further, because the FIG. 1 and FIG. 2 circuits require precise coordination of pointer delays and clock timing, placement of functional blocks in an integrated circuit layout during circuit layout fabrication of these FlFO memory devices is critical. For example, because the FIFO memory devices of FIGS. 1 and 2 are clock dependent in that they rely on delayed clock pulses to access data, such circuits are highly susceptible to clock glitches (i.e., errant clock pulses due to, for example, timing errors such as propagation delays). As described above, the possibility of data overwrite exists with the FIG. 1 circuit. Should a clock pulse appear at memory cell 6 prior to its occurrence at memory cell 8 due to a timing error resulting from improper placement of functional blocks in the FIFO memory devices, data stored in memory cell 8 would be overwritten. Further, during proper operation, a flip-flop of the FIG. 2B pointer circuit will generally pass the active pointer clockwise (i.e., to the right) by causing the flip-flops to be clocked in a counter-clockwise direction using delay gates 36-40. However, if flip-flop 37 were clocked before flip-flop 39 due to a timing error, the active pointer, if present in flip-flop 37, would be lost. More generally, whenever the flip-flop possessing the active pointer is clocked, a "0" will be clocked into that flip-flop and the active pointer will be lost. No further memory cells can then be addressed subsequently until the FIG. 2B pointer circuit is reset via line 42.
Circuit components which require precise timing to function properly are generally identified as having "critical" paths during circuit layout fabrication. As referenced herein, a "critical path" is an electrical interconnection between functional blocks which must not exceed a predetermined length. Should nodes which define the bounds of a critical path be spaced further than the predetermined length, RC delays due to the path itself can cause timing problems for the circuit component. All functional elements of the FIG. 1 and FIG. 2 FIFO circuits must therefore be placed within relatively close proximity on an integrated circuit layout to ensure that predetermined timing constraints will be satisfied.
Accordingly, there exists a need in the prior art for accurately inputting and outputting information of both asynchronous and synchronous devices such as FIFO memory devices in a fast, reliable manner which does not require the designation of critical paths during placement and routing of integrated circuit layout designs. For purposes of the present discussion, a synchronous device is one which requires use of a clock pulse having a given clock period, while an asynchronous device requires no such constraint.